The present invention relates generally to data communications between electronic devices and particularly, but not by way of limitation, to a receiver for high speed data communications.
Communication of binary digital data in electronic circuits often entails the transmission of complementary signals. Such signals are often referred to as differential signals since the data is propagated at both logic levels. In other words, one line may be at logic one and the other at logic zero. Signals may also be transmitted in single ended mode wherein both lines are at the same logic level, namely one-one or zero-zero. Single ended mode may be used during tristate, or high impedance, mode. During tristate mode, the bus is turned around and a different agent may be providing a driving signal.
Problems may arise when it becomes important to reliably distinguish between a single ended signal and a differential mode signal in transition from one state to another. For some receivers, receiving a single ended signal may trigger an unstable condition and cause the receiver output to become unpredictable. Further problems arise in that undesirable noise may blur the distinction between single ended and differential signals. Increasing the spread between a high and low logic level may provide an increased noise margins, however it may also frustrate the objective of communicating high speed data. Requiring the signal to switch across a greater voltage differential requires a longer time period and thus further slowing the speed of data transmission.
What is needed in the art is a system responsive to single ended input signals and differential input signals which is reliably operable at high data communication speeds.
The above mentioned problems associated with receivers, and other problems, are addressed by the present invention and will be understood by reading and studying the following specification.
In particular, an illustrative embodiment of the present invention includes a receiver having a reference input signal node for receiving a reference input signal, a first input signal node for receiving a first input signal, a second input signal node for receiving a second input signal concurrent with the first input signal, a first comparator coupled to the first input signal node, the second input signal node and the reference input signal node. The first comparator generates a first output and a second output based on the input signals. The receiver also includes a second comparator coupled to the first input signal node and the second input signal node. The second comparator generates a third output and fourth output based on the first input signal and the second input signal. The receiver also includes a logic array having a first input coupled to the first output, a second input coupled to the second output, a third input coupled to the third output, and a fourth input coupled to the fourth output. The logic has a first output signal node and a second output signal node wherein the first output signal node provides a first output signal and the second output signal node provides a second output signal. The first and second output signals are based on the first input, second input, third input and fourth input.
In one embodiment, the first comparator includes a first differential amplifier and a second differential amplifier. In one embodiment, the logic array includes a logical exclusive or gate. In one embodiment, the logic array includes a plurality of logical invertors. In one embodiment, the logic array includes a multiplexer.
One illustrative embodiment includes a circuit having a first differential amplifier, second differential amplifier and a third differential amplifier. The first differential amplifier includes a first output coupled to a first input of an exclusive or gate, a first input coupled to a first input node, and a second input coupled to a reference voltage. The second differential amplifier includes a first output coupled to a second input of the exclusive or gate, the exclusive or gate having an exclusive or gate output coupled to a first input of a first and gate, the exclusive or gate output further coupled to a first input of a second and gate. The second differential amplifier also includes a first input coupled to a second input node and a second input coupled to the reference voltage. The third differential amplifier includes a first output coupled to an input of a first delay, the first delay having an output coupled to a second input of the first and gate, the first and gate having an output coupled to a first output node. The third differential amplifier also includes a second output coupled to an input of a second delay, the second output having a state complementary to the first output of the third differential amplifier, the output of the second delay coupled to a second input of the second and gate, the second and gate having an output coupled to a second output node. The circuit also includes a first input coupled to the first input node and a second input coupled to the second input node.
In one embodiment, the first output of the first differential amplifier is delayed by a predetermined time period after receipt of a signal on the first input of the first differential amplifier and receipt of a signal on the second input of the first differential amplifier. In addition, the first output of the second differential amplifier is delayed by the predetermined time period after receipt of a signal on the first input of the second differential amplifier and receipt of a signal on the second input of the second differential amplifier. Furthermore, the first output of the third differential amplifier and the second output of the third differential amplifier is delayed by the predetermined time period after receipt of a signal on the first input of the third differential amplifier an d receipt of a signal on the second input of the third differential amplifier. In one embodiment, the reference voltage is between a voltage representing a logical one and a voltage representing a logical zero. In one embodiment, the reference voltage is substantially midway between a voltage representing a logical one and a voltage representing a logical zero. In one embodiment, the first delay comprises a first logic gate and the second delay comprises a second logic gate. In one embodiment, the first delay comprises a first plurality of series connected invertors and the second delay comprises a second plurality of series connected invertors. In one embodiment, the first delay has a first propagation delay time and the second delay has a second propagation delay time and the first propagation delay time is approximately equal to the second propagation delay time. In one embodiment, the first delay has a first propagation delay time and the exclusive or gate has a second propagation delay time and the first propagation delay time is approximately equal to the second propagation delay time. In one embodiment, the first output of the first differential amplifier changes state if the first input of the first differential amplifier and the second input of the first differential amplifier differs by a predetermined amount. In one embodiment, the first output of the first differential amplifier changes state if the first input of the first differential amplifier and the second input of the first differential amplifier differs by approximately 200 millivolts. In one embodiment, the first differential amplifier comprises a cross coupled latch having relatively large transistors.
One illustrative embodiment of the present invention includes a circuit having four differential amplifiers, an exclusive or gate, a nor gate, three delays, two and gates and two multiplexers. The first differential amplifier has a first output and two inputs, with one input coupled to a first input node and a second input coupled to a reference voltage. The second differential amplifier has an output and a first input coupled to a second input node and a second input coupled to the reference voltage. The exclusive or gate has a first and second input, with one input coupled to the first differential amplifier output and second input coupled to the second differential amplifier output. The nor gate has a first and second input coupled in parallel with the input to the exclusive or gate. The first delay is coupled between the nor gate output and the selector inputs to the first and second multiplexers. The third and fourth differential amplifier are each coupled to the first input node and to the second input node. The second delay is coupled to the third differential amplifier output and the third delay is coupled to the fourth differential amplifier output. The first and gate is coupled to the output of the second delay and to the exclusive or gate output. The second and gate is coupled to the output of the third delay and to the exclusive or gate output. The output of the first multiplexer is coupled to a first output node and a first input is coupled to the output of the first and gate output and the second input is coupled to a supply voltage. The output of the second multiplexer is coupled to a second output node and a first input is coupled to the output of the second and gate and a second input is also coupled to the supply voltage.
In one embodiment, the first delay includes a plurality of invertors. In one embodiment, the reference voltage is less than the supply voltage. In one embodiment, the reference voltage is approximately two thirds of the supply voltage. In one embodiment, the first differential amplifier, the second differential amplifier, the third differential amplifier and the fourth differential amplifier are approximately the same.
One illustrative embodiment of the present invention includes a method comprising receiving a first input signal, receiving a second input signal at a time concurrent with receipt of the first input signal, adding a predetermined time lag to the first input signal to create a delayed first input signal, and adding the predetermined time lag to the second input signal to create a delayed second input signal. The method continues with setting a first signal line based on a comparison of the delayed first input signal with the delayed second input signal, setting a second signal line based on the comparison of the delayed first input signal with the delayed second input signal, the second signal line complementary to the first signal line and setting a third signal line based on a comparison of the delayed first input signal with a reference signal. The method also includes setting a fourth signal line based on a comparison of the delayed second input signal with the reference signal, executing a logical exclusive or function using the third signal line and the fourth signal line to create a fifth signal, adding a predetermined delay to the first signal line to create a delayed first signal line, adding the predetermined delay to the second signal line to create a delayed second signal line, executing a logical and function using the fifth signal line and the delayed first signal line to create a first output, and executing a logical and function using the fifth signal line and the delayed second signal line to create a second output.
In one embodiment, the method provides that setting a first signal line includes processing using a differential amplifier. In one embodiment, setting a third signal line includes processing using a differential amplifier. In one embodiment, adding a predetermined delay includes executing a plurality of logical gates.